1. Field of the Invention
The invention relates to a phase-locked loop circuit (PLL circuit).
2. Description of the Related Art
FIG. 1 is a block diagram of a prior art PLL circuit. A voltage control oscillator 1 is a free-running oscillator which oscillates at a frequency corresponding to an input voltage. The oscillation frequency f.sub.V of the oscillator is divided by p ill a frequency divider 3, and then supplied as a signal V to a phase comparator 5. A reference signal generator 2 consists of, for example, a quartz oscillator. The output frequency of the reference signal generator is set so as to be lower than the oscillation frequency of the voltage control oscillator 1. The output frequency f.sub.R of the reference signal generator is divided by q in a frequency divider 4, and then supplied as a signal R to the phase comparator 5. The phase comparator 5 compares the two inputs with each other, and the comparison result is output to a low-pass filter 6. The low-pass filter 6 generates an analog voltage which corresponds to the extent of the comparison result, and feedbacks the analog voltage to the voltage control oscillator 1.
When the division ratio p:q of the frequency dividers 3 and 4 is set so that the frequency obtained by dividing the output frequency f.sub.V of the voltage control oscillator 1 by p in the frequency divider 3 equals to that obtained by dividing the output frequency f.sub.R of the reference signal generator 2 by q in the frequency divider 4, the following expression holds: EQU f.sub.V /p=f.sub.R /q (1)
In Ex. (1), EQU f.sub.V &gt;f.sub.R ( 2)
and, therefore, the following holds: EQU p&gt;q (3)
FIG. 2 is a circuit diagram showing a known example of the phase comparator 5 of FIG. 1. In the figure, a signal R is an input signal having a frequency which is obtained by dividing the output frequency f.sub.R of the reference signal generator 2 by q in the frequency divider 4, and a signal V is an input signal having a frequency which is obtained by dividing the output frequency f.sub.V of the voltage control oscillator 1 by p in the frequency divider 3. A signal U is an output signal of the phase comparator 5 which is output when the phase of the signal V lags that of the signal R, and a signal D is an output signal of the phase comparator 5 which is output when the phase of the signal V leads that of the signal R.
FIG. 3 is a timing chart showing the operation of the phase comparator 5 of FIG. 2. The signals U and D are "L" active. When the signals V and R are in-phase, both the signals U and D are "H". When the signal V lags the signal R, the signal U is "L" only during the period between the falling edge of the signal R and that of the signal V. When the signal V leads the signal R, the signal D is "L" only during the period between the falling edge of the signal V and that of the signal R. As seen from the above, the signals U and D are pulse signals having a time width which is equal to the phase difference between the signals R and V. During a period in which there is a phase difference, when the signal V leads, the signal D is output, and, when the signal V lags, the signal U is output. In other words, the signals U and D correspond to the frequency difference between the signals R and V, with the result that the deviation amount of the oscillation frequency of the voltage control oscillator 1 is converted into a time amount and then output as either of the signals U and D depending on the sign of the deviation. The signal U (D) is input to the low-pass filter 6 to be smoothed therein.
FIG. 4 is a circuit diagram showing an example of the low-pass filter 6 of FIG. 1. The signal U is input to the gate of a P-transistor 22, and the signal D is input to the gate of an N-transistor 23 via an inverter 21. The drains of the transistors 22 and 23 are connected to each other, and the junction point is connected to an output terminal via an active filter 24. In the active filter 24, a series circuit of a capacitor 25 and a resistor 26 is connected in parallel to an amplifier 27, and a resistor 28 is connected to one end of the parallel circuit.
When the signal U is "L" level, the P-transistor 22 is ON, and the capacitor 25 of the active filter 24 is charged. When the signal D is "L" level, the N-transistor 23 is ON, and the capacitor 25 is discharged. When both the signals U and D are "H" level, both the P-transistor 22 and the N-transistor 23 are OFF, and the charge held in the capacitor 25 remains to be held therein. When the total period of charge operations is long and the number of charge operations is large, the voltage of the output terminal becomes high, and this high voltage is feedbacked to the voltage control oscillator 1, with the result that the oscillation frequency is increased. When the total period of discharge operations is long and the number of discharge operations is large, the voltage of the output terminal becomes low, and this low voltage is feedbacked to the voltage control oscillator 1, with the result that the oscillation frequency is decreased. In the low-pass filter 6, as described above, the feedback voltage to the voltage control oscillator 1 is generated by processes of charging and discharging the capacitor 25. When the oscillation frequency of the voltage control oscillator 1 fluctuates, therefore, it requires a considerably prolonged period to return the oscillation frequency to the correct one.
Next, the operation of correcting the oscillation frequency f.sub.V which is deviated will be described. When the oscillation frequency f.sub.V of the voltage control oscillator 1 is decreased, the phase comparator 5 outputs the signal U which has information that the signal V (f.sub.V /p) lags the signal R (f.sub.R /q) and which indicates the phase difference between the signals. Accordingly, the capacitor 25 of the low-pass filter 6 is charged during the period in which the signal U is continued to be output, so that the feedback voltage is raised, with the result that the oscillation frequency f.sub.V of the voltage control oscillator 1 is increased.
When the oscillation frequency f.sub.V of the voltage control oscillator 1 is increased, the phase comparator 5 outputs the signal D which has information that the signal V leads the signal R and which indicates the phase difference between the signals. Accordingly, the capacitor 25 of the low-pass filter 6 is discharged during the period in which the signal D is continued to be output, so that the feedback voltage is lowered, with the result that the oscillation frequency f.sub.V of the voltage control oscillator 1 is decreased. This operation is repeated until Ex. (1) is satisfied, whereby the oscillation frequency F.sub.V is stabilized.
In the prior art PLL circuit described above, when the oscillation frequency f.sub.V of the voltage control oscillator 1 is deviated, the feedback voltage for correcting the deviation is generated depending on the charging and discharging characteristics of the capacitor 25 of the low-pass filter 6, thereby producing a problem in that a considerably prolonged time period must be elapsed until Ex. (1) is satisfied, or a problem of a reduced response. Furthermore, there is another problem in that, when the PLL circuit operates outside its operating range or runs away, it is difficult to control the operation of the PLL circuit.
In order to solve these problems, various methods have been proposed in which the output of a PLL circuit is digitized and the count value of a counter is converted into an analog value and then feedbacked to a voltage control oscillator. In the method disclosed in Japanese Patent Application Laid-Open No. 60-142622 (1985), the phase lead or phase lag is detected by an up-down counter, and the number of stages of an oscillator (ring oscillator) is changed. In the method disclosed in Japanese Patent Application Laid-Open No. 61-277211 (1986), the difference between the output frequency of a voltage control oscillator and a reference frequency is counted by an up-down counter, and a latch for setting the upper limit of the counter is provided to load the upper limit therein. In the method disclosed in Japanese Patent Application Laid-Open No. 3-211911 (1991), similarly, the difference between the output frequency of a voltage control oscillator and a reference frequency is counted by an up-down counter, and a correction value of a reference clock signal is calculated on the basis of the count value and previously stored characteristic data to obtain data of a control signal for feedback from the correction value. In the method disclosed in Japanese Patent Application Laid-Open No. 4-196715 (1992), a counter conducts the count operation in such a manner that, when the phase of an output signal of a voltage control oscillator lags that of a reference clock signal, the content is incremented, and, when the phase of the output signal leads that of the reference clock signal, the content is decremented, and the oscillation frequency of the voltage control oscillator is controlled by the output of the counter which has been converted into an analog value. Moreover, in the method disclosed in Japanese Patent Application Laid-Open No. 4-104519 (1992), a plurality of divided signals and an input signal from the outside are compared in phase with each other, and a control signal corresponding to the obtained phase difference is output to a voltage control oscillating unit. These prior art methods intend to provide a PLL circuit which has an excellent response or can rapidly recover the objective oscillation frequency.
When the supply of the reference signal is stopped, however, there arises a problem in that the whole of circuits including such a PLL circuit is disturbed and therefore it is impossible to control the circuits.
It is often that oscillation frequencies of a plurality of PLL circuits are switched so that they are used as sources for generating clock signals of higher and lower frequencies for a microcomputer. In such a case, there is a problem in that, when the frequency of a clock signal is switched to another one, a considerably prolonged time period must be elapsed until the oscillation frequency is stabilized and the starting of the microcomputer is delayed.